In order to control digital time division multiplexed (TDM) signal paths through a TDM switch, control signals are supplied to the switch from a so-called control memory. The control memory stores the TDM switch control signals, i.e., control word time slots, which control the route that each of the digital TDM signals traverses through the TDM switch.
Typically, random access memory (RAM) units have been employed for this purpose. In such prior known systems, proper correlation is obtained between time slots of the digital TDM signals being switched and corresponding control words from the RAM control memory by employing a sequential address generator which is synchronized to a TDM switching system timing signal. Control words are written into the RAM control memory and, then, read sequentially for each TDM switch data frame.
A problem with using a RAM memory unit for a TDM switch control memory is that a RAM is inefficient from capacity, size, power and cost standpoints. It just has more capacity and capability than is needed for the control memory task.
Shift registers have been used as memory units in such arrangements as digital signal processors, echo cancelers and the like. However, shift registers have not been used, heretofore, in a control memory for common control time division multiplexed switching systems because of synchronization problems and because the stored contents of the memory may be corrupted if synchronization is lost.